library IEEE;
use IEEE.std_logic_1164.all;

entity IDC_SEQ is
  port(
    CLK   : in  std_logic; -- sequencer clock
    RESET : in  std_logic; -- reset
    START : in  std_logic; -- sequencer start
    ACK   : in  std_logic; -- memory acknowledge
    MREQ  : out std_logic; -- memory request
    PC_W  : out std_logic; -- program counter write
    PC_R  : out std_logic; -- program counter read
    PC_INC: out std_logic; -- program counter increment
    AR_W  : out std_logic; -- address register write
    IR_W  : out std_logic; -- instruction register write
    DBI   : out std_logic  -- data bus buffer enable ( input )
  );
end IDC_SEQ;

architecture IDC_SEQ_BODY of IDC_SEQ is
	type   STATE_TYPE    is ( V0, V1, V2, F0, F1, DECO );
	signal PRESENT_STATE : STATE_TYPE;
begin
  SEQ_PROC : process( RESET, CLK )
  begin
    if RESET = '1' then		-- 非同期リセット
      PRESENT_STATE <= V0;	-- リセット時のステートはV0
    elsif CLK'event and CLK = '1' then
      case PRESENT_STATE is
        when V0 =>
          if START = '1' then	-- スタートがかかったらV1へ
            PRESENT_STATE <= V1;
          end if;
        when V1 =>		-- ACKが来たらV2へ
          if ACK = '1' then
            PRESENT_STATE <= V2;
          end if;
        when V2 => PRESENT_STATE <= F0;
        when F0 => PRESENT_STATE <= F1;
        when F1 =>		-- ACKが来たらDECOへ
          if ACK = '1' then
            PRESENT_STATE <= DECO;
          end if;
        when DECO => .........; -- 命令個別の処理へ
        ....
        when others => V0;	-- その他の条件
      end case;
    end if;
  end process;

  SEQ_CNTL : process( PRESENT_STATE )
  begin
    MREQ <= '0';		-- はじめに全てを初期化しておいて
    PC_W <= '0';   PC_R <= '0';   PC_INC <= '0';
    AR_W <= '0'; 
    IR_W <= '0';
    DBI  <= '0';
    case ( PRESENT_STATE ) is	-- 必要な制御信号のみ'1'へ設定
      when V0   => null;
      when V1   => MREQ <= '1';
      when V2   => MREQ <= '1';   PC_W <= '1';   DBI    <= '1';
      when F0   => PC_R <= '1';   AR_W <= '1';   PC_INC <= '1';
      when F1   => MREQ <= '1';
      when DECO => MREQ <= '1';   IR_W <= '1';   DBI    <= '1';
    end case;
end IDC_SEQ_BODY;